Memory, such as Dynamic Random Access Memory (DRAM), has become a major source of errors, particularly in data-heavy applications such as servers and datacenters. Techniques may be used to address error tolerance, such as chipkill level reliability (where a memory module is functional even if an entire DRAM device/chip in the module fails) and more aggressive error correction schemes such as double DRAM chip sparing, double device data correction, double chipkill (where a memory module will function even if two DRAM devices/chips in it fail), and chipkill with single bit error correction. However, such techniques are associated with deleterious effects, including high cost for increased DRAM redundancy (e.g., a need for a dedicated DRAM device/chip for storing error correcting code (ECC) per rank for chipkill error correction), high energy per access, and poor performance. Further, high fault tolerance requires accessing multiple DRAM memory modules to retrieve a single cacheline, which exacerbates over-fetch problems and increases energy needs per access. Most chipkill implementations cannot leverage more efficient ×16 or ×32 memory modules, and need less efficient ×4 or ×8 memory modules.